1. Field of the Invention
This document relates to a plasma display panel, more particularly, to a plasma display panel apparatus and manufacturing method of the same, which is capable of minimizing a gap between a seal layer and a UV Ultra Violet ray/silicon desiccant layer due to an air bubble, when the front panel and the rear panel of the plasma display panel are in the sealing process.
2. Description of the Background Art
As to the plasma display panel, the ultraviolet ray, which is generated when the inert mixing gas including He+Xe, Ne+Xe and He+Xe+Ne discharges, stimulates a fluorescent substance to display an image. PDP is available for a thin large-size product, in addition, an engineering development makes it possible to improve the picture quality.
FIG. 1 is a schematical diagram of a discharge cell cross section of a conventional plasma display panel.
As to FIG. 1, the plasma display panel is comprised of a scan electrode Y and a sustain electrode Z formed on the front panel not shown and data electrode 3X formed on the rear panel.
The scan electrode Y and sustain electrode Z are formed inparallel on the front panel not shown, including the wide transparent electrode 2Y, 2Z and the narrow bus electrode 1Y, 1Z. The transparent electrode 2Y, 2Z is formed with Indium-Tin-Oxide ITO which is a transparent conduction material, while the bus electrode 1Y,1Z is formed by patterning the silver Ag paste.
An upper-side dielectric layer not shown and a protective film not shown are laminated in order to cover the scan electrode Y and sustain electrode Z in the front panel. Wall charges generated by plasma discharge are stored in the upper-side dielectric layer. The protective film enhances the emission efficiency of the secondary electron with preventing the damage of the upper-side dielectric layer due to a sputtering generated in the plasma discharge. Generally, the magnesium oxide MgO is used as protective film. The data electrode X3 is orthognal with the scan electrode Y and sustain electrode Z.
The lower dielectric layer not shown and a rib 10 are formed in the rear panel. The red R, the blue B and the green G phosphor layer 20R, 20G, 20B are coated in the surface of the dielectric layer and rib 10 on the rear panel. The rib 10 prevents an optical and the electrical crosstalk between the discharge cells which are adjacent by separating discharge space horizontally adjacent. The phosphor layer 20R, 20G, 20B is excited with the ultraviolet ray generated by the plasma discharge to generate one visible ray among the red, the green and the blue.
The inert mixing gas including He+Xe, Ne+Xe and He+Xe+Ne is injected into the discharge space formed between the front panel, the rear panel and the rib 10.
FIG. 2 is a schematical diagram of the plane view of the whole panel shown in FIG. 1.
Referring FIG. 2, the conventional plasma display panel is divided into a panel display part L1 and a panel terminal part L2. Firstly, as described in FIG. 1, the panel display part L1 is formed with the identical structure. That is, the panel display part L1 is comprised of the seal material 201 for suturing the front panel 200 and rear panel 210 to form a discharge cell. The front panel 200 comprises a transparent electrode 2Y, 2Z, a bus electrode 1Y,1Z, a bus electrode pad 206, an upper-side dielectric layer not shown and a protective film not shown. The transparent electrode 2Y, 2Z forms a scan electrode Y and a sustain electrode Z which are formed in parallel on the front panel 200. The bus electrode 1Y, 1Z is formed in the edge of the transparent electrode 2Y, 2Z. The bus electrode pad 206 is extended from the bus electrode 1Y, 1Z to the panel terminal part L2. The upper-side dielectric layer not shown and the protective film not shown are successively laminated on the front panel 200 in order to cover the transparent electrode 2Y, 2Z, the bus electrode 1Y,1Z and the bus electrode pad 206. The data electrode 3X which is formed on the rear panel 210 in order to meet at right angle with the scan electrode Y or the sustain electrode Z. The data electrode 3X is extended to the data electrode pad 207. The data electrode pad 207 is comprised of the film type device such as Tape Carrier Package TCP 205 in which an integrated device is formed on the flexible printed circuit board supplying driving signal. The data electrode pad 207 and the film type device 205 in which the integrated device is formed on flexible printed circuit board is adhered with the anisotropic conductive film ACF not shown. The lower dielectric not shown laminated on the rear panel 210 is provided to cover data electrode 3X.
The panel terminal part L2 on the front panel 200 is comprised of the bus electrode pad 206 extending from the panel display part L1 and the flexible printed circuit board 204 which is connected to the bus electrode pad 206 to supply the driving signal. The bus electrode pad 206 and the flexible printed circuit board 204 are adhered with the anisotropic conductive film ACF not shown. The anisotropic conductive film has a film-type where the conductive particle such as a metal-coated plastic or a metal particle is dispersed, playing a role of electrically connecting the bus electrode 1Y,1Z and flexible printed circuit board 204.
The UV/silicon desiccant layer 203 is coated on the upper side to which the bus electrode 1Y, 1Z and the flexible printed circuit board 204 are connected.
The air bubble 202 or the gap is generated in the process of coating the seal layer 201 and UV/silicon desiccant layer 203 during the sealing of the plasma display panel. In the air bubble 202 region, due to the temperature change of the low temperature and the high temperature, the air expands or condenses. Therefore, the anti-wetting agent is detached or the air bubble is generated so that the exposed part is corroded by the external environment.
Moreover, as the viscosity of the UV/silicon desiccant layer 203 increases, it is unable to sufficiently seep between the interface. Thus, it causes a bad effect in the long-term reliability, because air bubble 202 is generated between the seal layer 201 and the UV/silicon desiccant layer 203.
Moreover, there is a problem in that the electrodes are damaged by the reaction with the external environment, such as temperature, moisture, corrosive gas source or a conductive material, that is, the reaction with the migration in the driving of plasma display panel, because the bus electrode 1Y, 1Z made of silver Ag is exposed to the external air on the panel terminal part L2.
FIG. 3 is a drawing showing the cross section in the line D1-D1′, D2-D2′, D3-D3′, D4-D4′ in FIG. 2.
Referring d1 of FIGS. 2 and 3, as to the cross-sectional view which cuts the right side of the plasma display panel in the line D1-D1′, the bus electrode pad 206 of the panel terminal part L2 is laminated on the upper side of the front panel 200 in the plasma display panel sealing. The seal layer 201 is formed between the rear panel 210 corresponding with the panel terminal part L2. The bus electrode pad 206 and the flexible printed circuit board 204 formed in the front panel 200 are adhered with the anisotropic conductive film ACF 310.
The UV/silicon desiccant layer 203 is coated onto the upper side to which the bus electrode pad 206 connected to the bus electrode 1Y, 1Z and the flexible printed circuit board 204 are connected.
The air bubble 202 region as much as 11 is generated in the process of coating the seal layer 201 and UV/silicon desiccant layer 203 in sealing the plasma display panel.
As to d2 shown in FIGS. 2 and 3, in the cross-sectional view which cuts the bottom plane of the plasma display panel in the line D2-D2′, the data electrode pad 207 of the panel display part L1 is laminated on the upper side of the rear panel 210, the seal layer 201 is formed between the front panel 200 and the rear panel 210 corresponding with the panel display part L1. The data electrode pad 207 formed on the rear panel 210 and the film type device TCP 205 in which the integrated device is formed on the flexible printed circuit board are adhered with the anisotropic conductive film ACF 310. The UV/silicon desiccant layer 203 is coated on the upper side in which data electrode pad 207 connected to the bus electrode 1Y, 1Z and the film type device TCP 205 in which the integrated device is formed on the flexible printed circuit board are connected.
In the process of coating with the seal layer 201 and UV/silicon desiccant layer 203, the air bubble region 202 as much as 12 is formed in the sealing of the plasma display panel.
As to d3 shown in FIGS. 2 and 3, in the cross-sectional view which cuts the left side of the plasma display panel in the line D3-D3′, the bus electrode pad 206 of the panel terminal part L2 is laminated on the upper side of the front panel 200, while the seal layer 201 is formed between the front panel 200 and the rear panel 210 corresponding with the panel terminal part L2. The bus electrode pad 206 formed in the front panel 200 is adhered with the anisotropic conductive film 310. The UV/silicon desiccant layer 203 is coated on the upper side in which the bus electrode pad 206 connected to the bus electrode 1Y, 1Z and the flexible printed circuit board 204 are connected.
The air bubble 202 region as much as 13 is generated in the process of coating the seal layer 201 and UV/silicon desiccant layer 203 in the sealing of the plasma display panel.
As to d4 shown in FIGS. 2 and 3, in the cross-sectional view which cuts the right side of the plasma display panel in the line D3-D3′, the data electrode pad 207 of the panel display part L1 is not laminated on the upper side of the rear panel 210 in sealing of plasma display panel. Therefore, also, the data electrode pad 207 formed on the rear panel 210, the flexible printed circuit board 204, the anisotropic conductive film ACF 310 and UV/silicon desiccant layer 203 are not coated.
As illustrated in d1 to d3 of FIG. 3, the air bubble 202 region delivers the stress to the UV/silicon desiccant layer 203 due to an expansion and condensation, the panel damage phenomenon is generated due to the anti-wetting agent exfoliation and the transmission of the panel stress, when the temperature changes to the low temperature or to the high temperature.